In order to drastically improve energy efficiency, we believe that future processor architectures should be customized with extensive use of accelerators from single-chip implementation to datacenter-level integration, as custom-designed accelerators often provide 10-1000X performance/energy efficiency over the general-purpose processors. Such an accelerator-rich architecture presents a fundamental departure from the classical von Neumann architecture, which emphasizes efficient sharing of the executions of different instructions on a common pipeline, providing an elegant solution when the computing resource is scarce. In constrast, the accelerator-rich architecture features heterogeneity and customizaiton for energy efficiency, which is better suited for energy-constrained designs where the silicon resource is abundant.
In this talk, I shall first present an overview of our research on customized computing, from single-chip, to server node, and to data centers, with extensive use of composable accelerators and field-programmable gate-arrays (FPGAs), and highlight our successes in several application domains. Then, I present our ongoing work on enabling automation for customized computing. One effort is on automated compilation for combining source-code level transformation for high-level synthesis with efficient parameterized architecture template generations. Another direction is to develop efficient runtime support for scheduling and transparent resource management for integration of FPGAs for datacenter-scale acceleration with support to the existing programming interfaces, such as MapReduce, Hadoop, and Spark, for large-scale distributed computation. I shall highlight the algorithmic challenges to many of these compilation and runtime optimization problems.
Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a Chancellor’s Professor at the UCLA Computer Science Department and the director of Center for Domain-Specific Computing (CDSC). He served as the department chair from 2005 to 2008. Dr. Cong’s research interests include synthesis of VLSI circuits and systems, energy-efficient computer architectures, reconfigurable systems, nanotechnology and systems, and highly scalable algorithms. He has over 400 publications in these areas, including 10 best paper awards, and the 2011 ACM/IEEE A. Richard Newton Technical Impact Award in Electric Design Automation. He was elected to an IEEE Fellow in 2000 and ACM Fellow in 2008. He is the recipient of the 2010 IEEE Circuits and System Society Technical Achievement Award "For seminal contributions to electronic design automation, especially in FPGA synthesis, VLSI interconnect optimization, and physical design automation."
Dr. Cong has graduated 32 PhD students. Nine of them are now faculty members in major research universities, including Cornell, Fudan Univ., Georgia Tech., Peking Univ., Purdue, SUNY Binghamton, UCLA, UIUC, and UT Austin. Dr. Cong has successfully co-founded three companies with his students, including Aplus Design Technologies for FPGA physical synthesis and architecture evaluation (acquired by Magma in 2003, now part of Synopsys), AutoESL Design Technologies for high-level synthesis (acquired by Xilinx in 2011), and Neptune Design Automation for ultra-fast FPGA physical design (acquired by Xilinx in 2013). Currently, he is a co-founder and the chief scitentific advisor of the Falcon Computing Solutions, a startup dedicated to enabling FPGA-based customized computing in cloud computing. Dr. Cong is also a distinguished visiting professor at Peking University.